Electromigration is a significant reliability failure mechanism for advanced semiconductor circuit interconnects. Electromigration is a well known phenomenon in which, generally speaking, atoms of a metal feature are displaced due to the electrical current passing through the feature. The migration of atoms can result in voids and/or hillocks in the feature, which can increase electrical resistance, cause shorts, and ultimately result in failure of the feature, which negatively impact reliability of the integrated circuit.
To prevent EM failure before a product lifetime, circuit designers typically abide by a maximum use current density (Juse) for metal vias and lines. The maximum use current density (Juse) is conventionally projected based on experimental stress data. For a predefined product end of life (EOL) failure target, chip level EM failure is determined by a failure probability of each circuit and the total number of circuits with EM concerns. Each circuit with EM concerns may contribute differently to the chip failure due to a different design current density and/or other EM characteristics such as redundancy.
As dimensions of features (e.g., pads, wires, interconnects, vias, etc.) continue to shrink to create smaller devices, the maximum allowable current density decreases rapidly due to electromigration (EM) effects. For example, operating voltages typically scale (e.g., get smaller) at a rate slower than metal lines, which results in higher current density in metal lines. As a result, it is difficult to maintain the same Juse for new generations of technology. The EM failure time of products decreases to almost half for each next generation at the same current density. Moreover, there is significant Juse degradation from generation to generation. Accordingly, there is a widening gap between design needs and what the technology currently supports.
Notwithstanding, products are trending toward longer power on hours (POH) and higher operating temperatures. This requires designers to produce products with better EM characteristics. One approach for improving the EM characteristics of a product involves improving the Juse, e.g., improving the current carrying capacity of the physical structures in the circuit. Another approach involves understanding possible fail sites and optimizing circuit design based upon such better understanding. However, there is no process for accurately estimating the number of potential fail sites (e.g., “critical elements”) in a semiconductor product. Instead, suppliers of IP layout elements typically provide generic estimations of numbers of critical elements in a one-size-fits-all approach. This type of approach is inadequate for accurately estimating EM-based reliability for products.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.